Education

  • Massachusetts Institute of Technology Cambridge, MA, PhD in Electrical Engineering
  • Massachusetts Institute of Technology Cambridge, MA, MS in Electrical Engineering
  • Purdue University West Lafayette, IN, BS in Electrical Engineering, with distinction

Associations

  • Registered to practice before the US Patent and Trademark Office
  • Ritwik has over seven years of experience in patent preparation and prosecution, as well as ten years of industry experience as an engineer or technical manager.
  • Ritwik is an inventor or co-inventor on 11 issued US patents, is an author or co-author on 40 conference or journal publications.

Patents

  • U.S. Patent No. 7,993,971, R. Chatterjee, E. Acosta, V. Mathew, “Forming a 3-D semiconductor die structure with an intermetallic formation.”
  • U.S. Patent No. 8,586,474, R. Chatterjee, V. Mathew, E. Acosta, S. Garcia, “A method to form a via.”
  • U.S. Patent No. 7,932,175, R. Chatterjee, V. Mathew, E. Acosta, S. Garcia, “A method to form a via.”
  • U.S. Patent No. 7,807,572, V. Mathew, R. Chatterjee, S. Garcia, E. Acosta, “Micropad formation for a semiconductor.”
  • U.S. Patent No. 8,003,517, V. Mathew, R. Chatterjee, S. Garcia, E. Acosta, “A method to form through silicon via for 3D interconnect applications.”
  • U.S. Patent No. 8,581,383, S. Pozder, R. Chatterjee, “3-D semiconductor die structure with containing feature and method.”
  • U.S. Patent No. 7,811,932, S. Pozder, R. Chatterjee, “3-D semiconductor die structure with containing feature and method.”
  • U.S. Patent No. 7,799,678, T. Kropewnicki, R. Chatterjee, K. Junker, “Method for forming a through silicon via layout.”
  • U.S. Patent Application Publication No. 20080113505, T. Sparks, S. Alam, R. Chatterjee, S. Rauf, “Method of forming a through substrate via.”
  • U.S. Patent No. 7,572,723, V. Mathew, R. Chatterjee, S. Garcia, E. Acosta, “Micropad for bonding and a method therefor.”
  • U.S. Patent No. 7,579,258, R. Chatterjee, “Semiconductor interconnect having adjacent reservoir for bonding and a method for formation.”
  • U.S. Patent No. 7,763,538, M. Turner, R. Chatterjee, S. Filipiak, “Dual plasma treatment barrier film to reduce low-k damage.”
  • U.S. Patent No. 7,422,979, L. Michaelson, E. Acosta, R. Chatterjee, S. Filipiak, S. Garcia, V. Mathew, “Method of forming a semiconductor device having a diffusion barrier stack and structure thereof.”

Ritwik Chatterjee, Ph.D. is a registered Patent Agent with extensive experience preparing and prosecuting patent applications before the U.S. Patent and Trademark Office. Ritwik holds B.S., M.S., and Ph.D. degrees in electrical engineering, and has 10 years of industry experience, primarily in the semiconductor industry, in addition to his more than 7 years of experience in patent preparation and prosecution. In addition to patent preparation and prosecution, Ritwik has substantial experience performing patent validity analyses and is a valuable asset in litigation support. An inventor or co-inventor in 11 issued US patents, he has authored or co-authored more than 40 journal or conference papers. Before beginning his career as a Patent Agent, Ritwik served various engineering or management roles at Intel, Eastman Kodak, Motorola Semiconductor, Freescale Semiconductor, and GeorgiaTech Packaging Research Center.